The MIPS-X RISC Microprocessor
The MIPS-X RISC microprocessor
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Only workspace and instruction pointers were saved in a context switch. For interrupts, the three stack registers also need to be saved. The workspace pointer register locates the local variables in memory. Transputers access words, except for byte and Boolean arrays. The Transputer could boot from ROM, or from a link, selectable by the state of a data pin. Booting from link allowed for fast initialization of a large collection of interconnected Transputers.
They were not code-compatible with other Intel products. They featured 32, bit register, with a priority interrupt controller, on-chip instruction cache lk to 16k , with data cache lk to 8k on some models, a PCI controller, and a memory controller on chip.
Some models included dual bit timers and an i2c bus. They were a superscalar architecture with register scoreboarding.
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Some models had an integral IEEE floating point unit. The processor is still in use for selected military applications. In order not to compete with its own i and i products in the general purpose computing market, Intel targeted the i to the embedded market. The i followed the Berkeley school of RISC design, with register windows and fast subroutine calls. The memory space was flat. The i addressed the high- end graphics and computation enhancement markets.
There were two members of the i family, the XR and the XP. The i processor achieved high levels of integer, floating point, and 3D graphics performance simultaneously. The iXR 32 achieved the same scalar performance and one fourth to one half of the vector performance of the first Cray machine, which is now in the Smithsonian. The era of the desktop supercomputer had arrived. The on- chip 8k data and 4k instruction caches had very high bandwidth due to wide internal data paths. The caches were two-way set-associative, and utilized a write-back scheme.
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The chip's external data bus was bits in width, but secondary cache was not supported. The chip was a Harvard architecture internally, but with a unified memory architecture externally. Dual instruction mode, in which a 64 bit wide integer and floating point pair is fetched and executed similtaneously, is a variation of the long instruction word fonnat. Intel's second-generation i, the XP, extended the edge of the performance envelope a considerable distance using 0.
The chip was binary compatible with the previous version, but doubled the performance figures by adding support for second level cache, faster busses, larger on-chip caches, as well as upping the clock speed. Multiprocessing support was added in the form of hardware support for bus snooping for cache consistency, and bus arbitration features.
The integer unit achieved the one instruction per clock goal. A single-cycle loop instruction was included. The integer unit could handle loads, stores, and loop control, while the floating point unit did multiplies and adds. The floating point unit used dedicated 3-stage pipelines for the add and multiply units. The unit supported the data types, operations, and exceptions defined in the IEEE standard format. The built-in 3D graphics unit also used pipelined techniques to speed up operations, such as management of Z-buffers, and color shading.
These techniques were used in shading and hidden line removal algorithms for high performance graphics. Display techniques such as pixel interpolation and Gouraud shading were supported by hardware graphics primitives, high speed floating point multiply, and vectorization of operations. In addition, the graphics unit could add and subtract bit integers. DMA handshake protocols also provided for multiprocessor bus mastership hand off. A single interrupt pin was provided, and the external interrupt could be masked in software. The i mmu design was borrowed from the i family.
The XR included hardware support for cache consistency, bus snooping, and arbitration. The i bus architecture was Harvard internally, unified externally. Bus width was 64 bits. On- chip write buffers were used. The program initialized control registers, and the caches were flushed, although they were marked as invalidated.
Execution began at the supervisor level. The secondary cache was unified. Cache write-through was supported. In the i instruction set, all instructions were bits in size, and either a register or a control fonnat.
The integer math instructions included add and subtract on up to 32 bit entities. Floating point instructions included add, subtract, multiply, reciprocal, square root, compares and conversions. Flow control instructions included call subroutine, branch conditional and unconditional, and a software trap instruction. Special graphics instructions supported Z-buffer and pixel operations. On the i chips were 32 bit integer registers and 32 bit floating point registers. R0 was read as zero, as were F0 and FI.
There were twelve control registers, including the processor status register PSR , the floating point status register FSR , the extended PSR EPSR , the data breakpoint register DB , the directory base register, the fault instruction register, the bus error address register, the concurrency control register, and 4 privilege registers P0-P4. In addition, 5 trap flags were included. The other fields were Delayed Switch, dual instruction mode, and a kill-next-floating-point instruction. The EPSR contained more infonnation about the state, including the processor type and stepping number manufacturing variation , endian setting, on-chip data cache size, bus error flag, overflow flag, trap indicators for delayed instruction, auto increment, and pipeline usage, a write- protect bit for the directory and page table entries, and interlock bit for trap sequences.
The floating point status register contained information about the current state of the floating point processor, including rounding modes, trap status, overflow and underflow from the adder 34 or multiplier, and trap enables. The data breakpoint register stored the breakpoint address if a trap was taken. The Directory base register was used to control caching, address translation and bus options. The fault instruction register was used to hold the address of the instruction causing a trap.
Similarly, the bus error address register held the address for the bus cycle during which a bus error or parity error was detected. The concurrency control register was used to enable or disable the concurrency control feature for multiprocessing, and to specify the controlled address space. Byte ordering was selectable in software, with the normal mode being little-endian. The controlling bit was contained in the extended PSP register.
In the i, most data types were compatible with those of the 80x86 family. Data types included 8- to bit integers, and , , or bit floating point operands. The iXP pixel processor operated on 8-, , or bit data items. In a bit wide pixel, there were 6 bits of intensity for red and green, and 5 bits for blue.